gronod
a33b4b0c74
ci / test (push) Successful in 1m4s
ci / firmware (jc4827w543, sdkconfig.s3, esp32s3) (push) Successful in 3m56s
ci / firmware (wroom, sdkconfig.wroom, esp32) (push) Successful in 3m57s
ci / test (pull_request) Successful in 1m22s
ci / firmware (wroom, sdkconfig.wroom, esp32) (pull_request) Successful in 4m42s
ci / firmware (jc4827w543, sdkconfig.s3, esp32s3) (pull_request) Successful in 4m47s
24 lines
1.3 KiB
Markdown
24 lines
1.3 KiB
Markdown
STATUS: DONE
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DEPENDS: none
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**READ:** `docs/megaplans/INTEGRATION-MEGAPLAN.md`, `docs/JC4827W543_PIN_AUDIT_VERIFIED.md`, `components/board_jc4827w543/board.c`, `components/board_wroom/board.c`
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**IN:**
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1. `board_jc4827w543`: add `board_pin_motor_step()` → 16, `board_pin_motor_dir()` → 15, `board_pin_temp()` → 17, `board_pin_spk_bclk()`, `board_pin_spk_lrclk()`, `board_pin_spk_din()` → 42, 2, 41; change `board_pin_motor_en()` → 7 (keep disable level 1 = active-LOW EN).
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2. `board_wroom`: add matching `board_pin_motor_step()` → 12, `board_pin_motor_dir()` → 14, `board_pin_temp()` → 13 so HAL impls can be shared.
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3. Update `docs/CURRENT_STATE.md` pin table note and `JC4827W543_PIN_AUDIT_VERIFIED.md` header section with the corrected labels if not already updated (P2: IO46/9/14/5, P3: IO6/7/15/16, P4: GND/3V3/17/18).
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**OUT:** HAL implementations, business logic, NVS profiles.
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**FORBIDDEN:** GPIO46 for any output; stealing TF, QSPI, GT911, USB, or UART0 pins.
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**VERIFY:** `idf.py build` succeeds for both `esp32` and `esp32s3` targets.
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**COMMITS:**
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1. `Lock S3 header pins and introduce shared board pin accessors`
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2. `Update pin audit documentation labels`
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**DoD checkboxes:**
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- [ ] `board_jc4827w543` pin accessors added.
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- [ ] `board_wroom` pin accessors added.
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- [ ] Build succeeds on both targets.
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