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added support fo guition board

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gronod
2026-03-13 16:39:27 +00:00
parent 0203682200
commit c5233cf15c
16 changed files with 1293 additions and 4 deletions
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161
components/display/core/ifaces/default_if_qspi.c Normal file
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/**
* QSPI Interface for Guition JC4827W543C ILI9488 Display
* Supports ESP32-S3 QSPI peripheral
*
* (c) Guition Support 2026
* This software is released under the MIT License.
* https://opensource.org/licenses/MIT
*/
#include <stdio.h>
#include <stdint.h>
#include <stdbool.h>
#include <string.h>
#include <driver/spi_master.h>
#include <driver/gpio.h>
#include <freertos/task.h>
#include "gds.h"
#include "gds_err.h"
#include "gds_private.h"
#include "gds_default_if.h"
static const int GDS_QSPI_Command_Mode = 0;
static const int GDS_QSPI_Data_Mode = 1;
static spi_host_device_t QSPIHost;
static int DCPin;
static bool QSPIDefaultWriteBytes( spi_device_handle_t QSPIHandle, int WriteMode, const uint8_t* Data, size_t DataLength );
static bool QSPIDefaultWriteCommand( struct GDS_Device* Device, uint8_t Command );
static bool QSPIDefaultWriteData( struct GDS_Device* Device, const uint8_t* Data, size_t DataLength );
bool GDS_QSPIInit( int QSPI, int DC ) {
QSPIHost = QSPI;
DCPin = DC;
return true;
}
bool GDS_QSPIAttachDevice( struct GDS_Device* Device, int Width, int Height, int CSPin, int RSTPin, int BackLightPin, int Speed, int Mode ) {
spi_device_interface_config_t QSPIDeviceConfig = { };
spi_device_handle_t QSPIDevice;
NullCheck( Device, return false );
if (CSPin >= 0) {
ESP_ERROR_CHECK_NONFATAL( gpio_set_direction( CSPin, GPIO_MODE_OUTPUT ), return false );
ESP_ERROR_CHECK_NONFATAL( gpio_set_level( CSPin, 0 ), return false );
}
QSPIDeviceConfig.clock_speed_hz = Speed > 0 ? Speed : SPI_MASTER_FREQ_20M;
QSPIDeviceConfig.spics_io_num = CSPin;
QSPIDeviceConfig.queue_size = 4;
QSPIDeviceConfig.mode = Mode;
QSPIDeviceConfig.flags = SPI_DEVICE_HALFDUPLEX;
QSPIDeviceConfig.duty_cycle_pos = 128; // 50% duty cycle
// QSPI specific configuration for ESP32-S3
QSPIDeviceConfig.command_bits = 8;
QSPIDeviceConfig.address_bits = 24;
QSPIDeviceConfig.address_len = 3;
if( spi_bus_add_device( QSPIHost, &QSPIDeviceConfig, &QSPIDevice ) != ESP_OK ) {
GDS_LOG_ERROR( "Failed to add QSPI device to host" );
return false;
}
if( DCPin >= 0 ) {
ESP_ERROR_CHECK_NONFATAL( gpio_set_direction( DCPin, GPIO_MODE_OUTPUT ), return false );
ESP_ERROR_CHECK_NONFATAL( gpio_set_level( DCPin, 1 ), return false );
}
if( RSTPin >= 0 ) {
ESP_ERROR_CHECK_NONFATAL( gpio_set_direction( RSTPin, GPIO_MODE_OUTPUT ), return false );
ESP_ERROR_CHECK_NONFATAL( gpio_set_level( RSTPin, 1 ), return false );
}
if( BackLightPin >= 0 ) {
ESP_ERROR_CHECK_NONFATAL( gpio_set_direction( BackLightPin, GPIO_MODE_OUTPUT ), return false );
ESP_ERROR_CHECK_NONFATAL( gpio_set_level( BackLightPin, 1 ), return false );
}
Device->WriteCommand = QSPIDefaultWriteCommand;
Device->WriteData = QSPIDefaultWriteData;
Device->DeviceHandle = QSPIDevice;
// Hardware reset if pin is available
if( RSTPin >= 0 ) {
gpio_set_level( RSTPin, 0 );
vTaskDelay( pdMS_TO_TICKS( 10 ) );
gpio_set_level( RSTPin, 1 );
vTaskDelay( pdMS_TO_TICKS( 120 ) );
}
return true;
}
static bool QSPIDefaultWriteCommand( struct GDS_Device* Device, uint8_t Command ) {
return QSPIDefaultWriteBytes( Device->DeviceHandle, GDS_QSPI_Command_Mode, &Command, 1 );
}
static bool QSPIDefaultWriteData( struct GDS_Device* Device, const uint8_t* Data, size_t DataLength ) {
if( DCPin >= 0 ) {
gpio_set_level( DCPin, 1 );
}
bool Result = QSPIDefaultWriteBytes( Device->DeviceHandle, GDS_QSPI_Data_Mode, Data, DataLength );
if( DCPin >= 0 ) {
gpio_set_level( DCPin, 0 );
}
return Result;
}
static bool QSPIDefaultWriteBytes( spi_device_handle_t QSPIHandle, int WriteMode, const uint8_t* Data, size_t DataLength ) {
spi_transaction_ext_t SPITransaction = { };
SPITransaction.base.flags = SPI_TRANS_VARIABLE_CMD | SPI_TRANS_VARIABLE_ADDR | SPI_TRANS_VARIABLE_DUMMY;
SPITransaction.base.cmd = 0;
SPITransaction.base.addr = 0;
SPITransaction.base.length = DataLength * 8;
SPITransaction.base.tx_buffer = Data;
SPITransaction.base.rx_buffer = NULL;
SPITransaction.command_bits = 8;
SPITransaction.address_bits = 0;
SPITransaction.dummy_bits = 0;
if( WriteMode == GDS_QSPI_Command_Mode ) {
SPITransaction.command_bits = 8;
SPITransaction.base.cmd = Data[0];
SPITransaction.base.length = 0;
SPITransaction.base.tx_buffer = NULL;
}
if( spi_device_transmit( QSPIHandle, (spi_transaction_t*) &SPITransaction ) != ESP_OK ) {
GDS_LOG_ERROR( "QSPI transaction failed" );
return false;
}
return true;
}
bool GDS_QSPIBusInit( int MOSIPin, int MISOPin, int CLKPin, int Host ) {
spi_bus_config_t BusConfig = { };
NullCheck( Host >= SPI2_HOST && Host <= SPI3_HOST, return false );
// QSPI pin configuration for ESP32-S3
BusConfig.mosi_io_num = MOSIPin;
BusConfig.miso_io_num = MISOPin;
BusConfig.sclk_io_num = CLKPin;
BusConfig.quadwp_io_num = -1; // Not used for ILI9488
BusConfig.quadhd_io_num = -1; // Not used for ILI9488
BusConfig.max_transfer_sz = 65536;
BusConfig.flags = SPICOMMON_BUSFLAG_MASTER | SPICOMMON_BUSFLAG_NATIVE_PINS;
if( spi_bus_initialize( Host, &BusConfig, DMA_CH_AUTO ) != ESP_OK ) {
GDS_LOG_ERROR( "Failed to initialize QSPI bus" );
return false;
}
return true;
}